Cypress Semiconductor /psoc63 /PERI /GR[1] /SL_CTL

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Interpret as SL_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLED_0)ENABLED_0 0 (ENABLED_1)ENABLED_1 0 (ENABLED_2)ENABLED_2 0 (ENABLED_3)ENABLED_3 0 (ENABLED_4)ENABLED_4 0 (ENABLED_5)ENABLED_5 0 (ENABLED_6)ENABLED_6 0 (ENABLED_7)ENABLED_7 0 (ENABLED_8)ENABLED_8 0 (ENABLED_9)ENABLED_9 0 (ENABLED_10)ENABLED_10 0 (ENABLED_11)ENABLED_11 0 (ENABLED_12)ENABLED_12 0 (ENABLED_13)ENABLED_13 0 (ENABLED_14)ENABLED_14 0 (ENABLED_15)ENABLED_15

Description

Slave control

Fields

ENABLED_0

Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO register slave (PPU structures) and is a constant ‘1’. This slave can NOT be disabled.

ENABLED_1

Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant ‘0’) and its resets are activated.

Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant ‘1’ (SW: R): the slave can NOT be disabled.

ENABLED_2

Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (constant ‘0’) and its resets are activated.

Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant ‘1’ (SW: R): the slave can NOT be disabled.

ENABLED_3

N/A

ENABLED_4

N/A

ENABLED_5

N/A

ENABLED_6

N/A

ENABLED_7

N/A

ENABLED_8

N/A

ENABLED_9

N/A

ENABLED_10

N/A

ENABLED_11

N/A

ENABLED_12

N/A

ENABLED_13

N/A

ENABLED_14

N/A

ENABLED_15

N/A

Links

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